1. Field of the Invention
Embodiments of the invention relate generally to non-volatile semiconductor memory devices. More particularly, embodiments of the invention relate to non-volatile semiconductor memory devices including phase-change memory cells.
This application claims priority to Korean Patent Application No. 10-2006-0024328, filed on Mar. 16, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Non-volatile memories can be found in a wide variety of consumer and industrial electronic devices such as cellular phones, personal computers, cameras, and personal digital assistants, to name but a few. An important property of non-volatile memories is their ability to retain stored data when disconnected from a power source. This property allows the non-volatile memories to conserve power, and it also reduces the risk of data loss in the event of unanticipated power failure.
Perhaps the most common form of non-volatile memory currently is flash memory. Flash memory is a popular choice for auxiliary memories of portable electronic devices for a variety of reasons, including its non-volatile properties, speed, high degree of integration, and high tolerance to physical shock.
Compared with other forms of memory such as dynamic random access memory (DRAM), flash memory has similar read times, but significantly slower write times. For example, a typical read time for a flash memory cell varies between 20 and 120 ns, while a typical read time for a DRAM cell is about 50 ns. On the other hand, a typical write time for a flash memory cell is greater than 1 μs, while a typical write time for a DRAM cell is about 50 ns.
Another difference between flash memory and other forms of memory is its endurance. On average, a flash memory cell can only be erased or rewritten on the order of 105 times before the cell fails. In contrast, DRAM cells can be erased or rewritten on the order of 1015 times without failure.
Because of flash memory's relatively long write times and low endurance, researchers have looked to alternative technologies for next generation non-volatile memories. Among the more promising alternatives, there are ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and Phase-Change Random Access Memory (PRAM). Each of these alternatives tends to have read and write times less than 100 ns and endurance on the order of 1013 or greater. In addition, each of the above alternatives tends to have a lower operating current than flash memory.
A PRAM, also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to energy (e.g., thermal energy) so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
Figures (FIGS.). 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively. In this example, the memory cell 10 includes a phase-change resistive element 11 and a transistor 19 connected in series between a bit line BL and a reference potential (e.g., ground), with the transistor 19 being gated to a word line WL. A more simplified diagram of memory cell 10 is shown for example, in FIG. 2. It should be noted that FIGS. 1A, 1B, and 2 are general schematic views only, that the configuration of phase-change resistive element 11 is presented as an example only, and that other configurations and connections with respect to phase-change resistive element 11 are possible. For example, phase-change resistive element 11 may instead be connected in series with a diode 32 between bit line BL and word line WL, as shown in FIG. 3.
The memory cell shown in FIG. 2 is generally referred to as a metal oxide semiconductor (MOS) type PRAM cell, and the memory cell shown in FIG. 3 is generally referred to as a diode-type PRAM cell. Differences between the MOS type PRAM cell and the diode type PRAM cell include, for example, the cell size and required driving current. The diode type PRAM cell is generally smaller, and requires a higher driving current than the MOS type PRAM cell.
In each of FIGS. 1A and 1B, phase-change resistive element 11 includes a top electrode 12 formed on a phase-change material 14. In this example, top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between phase-change material 14 and a conductive bottom electrode 18. Access transistor 19 is electrically connected between bottom electrode 18 and the reference potential. As already suggested, the gate of access transistor 19 is electrically connected to word line WL of the PRAM cell array (not shown).
In FIG. 1A, phase-change material 14 is illustrated as being in its crystalline state. As described previously, this means that memory cell 10 is in a low-resistance ‘set’ state or logic ‘0’ state. In FIG. 1B, a portion of phase-change material 14 is illustrated as being amorphous. Again, this means that memory cell 10 is in a high-resistance ‘reset’ state or logic ‘1’ state.
The set and reset states of memory cell 10 of FIGS. 1A and 1B are established by controlling the magnitude and duration of current flow through BEC 16. That is, phase-change resistive element 11 is activated (or accessed) by operation of access transistor 19 which is responsive to a voltage of word line WL. When activated, memory cell 10 is programmed according to the voltage of bit line BL. The voltage of bit line BL is controlled to establish a programming current ICELL which causes BEC 16 to act as a resistive heater which selectively programs phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 4 illustrates an example of temperature pulse characteristics of phase-change material as the phase-change material is programmed in the ‘set’ and ‘reset’ states. In particular, reference number 41 denotes the temperature pulse of the phase-change material programmed to its ‘reset’ state, and reference number 42 denotes the temperature pulse of the phase-change material programmed to its ‘set’ state.
As shown in FIG. 4, when the phase-change material is programmed to its ‘reset’ state, the temperature of the material is increased above its melting temperature Tm (e.g., 610° C.) for a relatively short period of time, and then allowed to rapidly cool. In contrast, when the phase-change material is programmed to its ‘set’ state, the temperature of the material is increased to below its melting point Tm and above its crystallizing temperature Tx (e.g., 450° C.) for a longer period of time, and then allowed to cool more slowly. The fast and slow cooling of the ‘reset’ and ‘set’ programming operations are referred to in the art as fast “quenching” and slow “quenching”, respectively. The temperature range between the melting temperature Tm and the crystallizing temperature Tx is referred to as the “set window.”
FIG. 5 is a graph illustrating the resistive characteristic (current versus voltage) of a phase-change material for each of its ‘set’ and ‘reset’ states. In particular, line 51 is representative of the resistive characteristic of a phase-change material in its ‘set’ state, and line 52 is representative of the same in its ‘reset’ state. As shown, the set and reset resistances differ substantially below a threshold voltage (e.g., 1v), but become substantially equal to one another above the threshold voltage. In order to maintain the necessary sensing margin during reading operations, it is necessary to restrict the voltage of bit line BL to a region below the voltage threshold. As explained below with reference to FIG. 6, a clamping transistor inserted in bit line BL may be used for this purpose.
FIG. 6 is a simplified circuit diagram for explaining write and read operations of the phase-change memory cell. As shown, a bit line BL is coupled to a write driver 63 and a read circuit 64. Also connected to bit line BL are phase-change memory cell 10, a pre-charge transistor 61, and a select transistor 62.
In this example, phase-change memory cell 10 includes a phase-change element and transistor connected in series between the bit line BL and a reference potential (e.g., ground), where the transistor is gated to a word line WL. As suggested previously, other configurations of the phase-change memory cell 10 are possible. For example, phase-change memory cell 10 may instead include a phase-change memory element and diode connected between bit line BL and word line WL.
As those skilled in the art will appreciate, precharge transistor 61 (gated to a precharge control signal PREBL) is used to precharge bit line BL in a read and/or write operation, while select transistor 62 (gated to a y-address signal YSEL) is used to activate bit line BL.
Write driver 63 typically includes a current mirror 65 for applying either a reset current RESET or a set current SET as a write current iwrite to bit line BL during a write operation. Reset current RESET and set current SET were discussed previously in connection with FIG. 4.
Read circuit 64 is functional in a read operation to apply a read current tread from a current source READ to bit line BL. A clamping transistor 66, which is gated to a clamp control signal VCLAMP, restricts bit line BL voltage to a region below the voltage threshold discussed above in connection with FIG. 5. A sense-amplifier S/A compares the voltage of bit line BL with a reference voltage VREF, and outputs the comparison result as output data OUT.
As with other types of non-volatile memory devices, there are a variety of ways to organize and operate phase-change memory cells and associated circuitry within a PRAM memory architecture to improve overall system performance. One technique, which is commonly used in NOR flash memories, is known as a read-while-write (RWW) memory. A RWW memory comprises a memory array divided into one or more banks, where each bank has its own set of sense amplifiers and functions like an independent chip. For example, data can be read from one bank while data is being written to another bank.
FIG. 7 shows an exemplary RWW memory comprising a memory array 70 divided into four (4) banks BANK0 through BANK3,where each one of the four banks BANK0 through BANK3 includes (8) eight blocks, BLOCK0 through BLOCK7. The simultaneous read-while-write capability of the RWW memory can be advantageously used, for example, by storing frequently read data such as program code in one bank while reserving space in another memory bank for temporary data storage. No I/O interfaces for memory array 70 are shown in FIG. 7; however, RWW memories generally have the same pinout as a conventional NOR flash memory.
As shown in FIG. 7, each bank comprises a plurality of blocks, where each block comprises a plurality of memory cells. In a typical RWW memory, data is read or programmed in units of multiple memory cells. For example, in a RWW NOR flash memory, data is read or programmed in units of bytes or words, and erased an entire block at a time.
Although RWW memories allow data to be read from one bank while data is written to another bank, simultaneous read and write operations cannot be performed on the same bank. In flash memory devices, this creates a serious performance problem because the time it takes to write data to a flash memory cell tends to be significantly larger than the time it takes read data from a flash memory cell. As a result, a read operation for one address in a bank may be substantially delayed while waiting for a write operation to another address in the same bank to finish.
To address this problem, researchers have developed a technique for temporarily suspending a write operation in a flash memory to allow a read operation to proceed without substantial delay. This technique is referred to as a write-suspend-read, or program-suspend-read operation. FIG. 8 is a waveform timing diagram illustrating one way to perform a write-suspend-read operation in a flash memory cell.
Referring to FIG. 8, a program signal PGM indicates a time tPGM required to program a flash memory cell, or a unit program block write period. For instance, program signal PGM could be a program voltage applied to the flash memory cell while it is being programmed. In the absence of an intervening read operation, the program operation is performed in one continuous interval, as indicated by the waveform labeled “normal write timing” in FIG. 8. However, where there is an intervening read operation for another address in the same bank as the flash memory cell being programmed, a suspend signal PGM_SUSPEND is asserted, causing the program operation to be temporarily suspended after a time tPGM—PRE. The read operation is then executed, and then following the read operation, a resume signal PGM_RESUME is asserted, causing the program operation to continue for a time tPGM-tPGM—PRE. The timing for program signal PGM when there is an intervening read operation is shown by a waveform labeled “Write suspend/resume timing” in FIG. 8.
Even when the program operation is interrupted as illustrated in FIG. 8 the total time required to perform the program operation does not change. In other words, the flash cell is programmed according to the cumulative time that program signal PGM is asserted before and after the read operation.
Various flash memory cells allowing a read operation to interrupt a program interruption are disclosed, for example, in U.S. Pat. No. 5,287,469 to Tsuboi, U.S. Pat. No. 5,822,244 to Hansen et al., and U.S. Pat. No. 6,930,925 to Guo et al.
Like flash memory cells, phase-change memory cells can generally be read much faster than they can be programmed (i.e., “set” or “reset”). Accordingly, it may be advantageous to interrupt a program operation to one address in a bank of a phase-change memory cell in order to perform a read operation from another address in the same bank. However, unlike flash memory cells, programming of a phase-change memory cell must start over from the beginning after an interruption occurs. In other words, the time that a phase-change material is heated, as illustrated by the temperature pulse characteristics of FIG. 4, does not accumulate across interruptions.
Also unlike flash memory cells, an entire block of phase-change memory cells generally cannot be programmed or erased at the same time. Simultaneously programming or erasing an entire block of phase-change memory cells requires an untenably large drive current. Accordingly, a block of phase-change memory cells is typically programmed sequentially by applying a series of program pulses to the respective cells.
Because phase-change memory cells have different programming requirements than conventional flash memory cells, the techniques commonly used to operate-flash memory devices are simply not applicable to operation of a PRAM device.